Phase-locked-loops (PLLs) are useful in a variety of applications and are particularly useful for frequency synthesis. FIG. 1 illustrates a conventional PLL such as may be used for frequency synthesis. A phase-and-frequency detector (PFD) receives a reference clock signal CKref at a defined frequency Fref and also a feedback signal, SFB, which is derived from the output of the PLL and which thus has a frequency FFB related to the output of the PLL. The PFD generates adjustment signals for controlling a charge pump 102. The adjustment signals are generally referred to as up and down signals, U and D, as they generally result in steering the frequency of the PLL upwards or downwards respectively. The output of the charge pump 102 is smoothed by a loop filter 103 and the resultant voltage drives a voltage-controlled-oscillator (VCO) 104, which generates the output signal, Sout, from which the feedback signal SFB is derived.
If the edges, i.e. signal transitions, of the feedback signal, SFB, are lagging behind corresponding edges of the reference clock signal CKref, then control pulses are generated in the up signal to provide positive current pulses at the current output from the charge pump, and hence increase the filtered voltage received by the VCO and provide upwards frequency steering. Likewise if edges of the feedback signal, SFB, are appearing in advance of corresponding edges of the reference signal CKref, then control pulses generated in the down signal D to provide downwards frequency steering in a similar but opposite manner. When the frequency of the feedback signal is close to the reference frequency the control pulses of the up or down signals will have a pulse width, i.e. a duration, related to the extent to which the feedback signal lags or leads the reference clock signal CKref respectively, i.e. the phase difference between the feedback signal versus the reference clock signal. The overall result is convergence to a phase lock of the reference clock signal and the feedback signal and thus also a frequency lock.
The output signal Sout from the VCO 104 may be input into a frequency divider 105 which may be operated to provide a selected divide by N function. The output from the frequency divider 105 is used as the feedback signal SFB. In this way an output signal Sout with a frequency Fout that is a selected integer multiple N of the frequency Fref of the reference clock signal CKref can be synthesised by selecting the suitable divisor N for the frequency divider.
In a conventional PLL such as illustrated in FIG. 1 the components of the charge pump 102 and loop filter 103 are analogue, for instance the charge pump may comprise current sources and the loop filter may be a resistor-capacitor filter. Such analogue components can require significant area of a semiconductor die in an integrated circuit implementation, with a resulting impact in size and thus cost of the PLL.
All-digital PLLs have been proposed where the functionality of the PFD and charge pump is effectively replaced by a Time-to-Digital Converter (TDC). The TDC receives a feedback signal of the output from the PLL and basically counts the number of cycles of a fast system clock to provide a digital value indicative of the pulse width or duration being output from the PLL. This allows digital filtering and processing and a digitally-controlled-oscillator (DCO) can be used to provide the output signal Sout. In such an approach however the accuracy of measurement of the frequency FFB of the feedback signal depends on the speed of the fast system clock. A relatively slow system clock leads to relatively high quantisation error. A very fast system clock is thus required to provide acceptable performance but a fast system clock adds to the power consumption, which may be a significant issue especially for circuits intended for battery powered devices and there are technical challenges associated with counters running with very fast clocks.